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Perez et al 2019, Toward Reliable Multi-Level Operation in RRAM Arrays.pdf3.81 MBAdobe PDFView/Open
Title: Toward Reliable Multi-Level Operation in RRAM Arrays: Improving Post-Algorithm Stability and Assessing Endurance/Data Retention
Authors: Perez, E.Zambelli, C.Mahadevaiah, M.K.Olivo, P.Wenger, C.
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Issue Date: 2019
Published in: IEEE Journal of the Electron Devices Society Vol. 7 (2019)
Publisher: Piscataway : Institute of Electrical and Electronics Engineers Inc.
Abstract: Achieving a reliable multi-level operation in resistive random access memory (RRAM) arrays is currently a challenging task due to several threats like the post-algorithm instability occurring after the levels placement, the limited endurance, and the poor data retention capabilities at high temperature. In this paper, we introduced a multi-level variation of the state-of-the-art incremental step pulse with verify algorithm (M-ISPVA) to improve the stability of the low resistive state levels. This algorithm introduces for the first time the proper combination of current compliance control and program/verify paradigms. The validation of the algorithm for forming and set operations has been performed on 4-kbit RRAM arrays. In addition, we assessed the endurance and the high temperature multi-level retention capabilities after the algorithm application proving a 1 k switching cycles stability and a ten years retention target with temperatures below 100 °C.
Keywords: Compliance control; Stability; Accelerated tests; Algorithm stability; arrays; Data retention; Multilevels; Resistive random access memory (rram); State of the art; Verify algorithms; RRAM; accelerated test; algorithm instabilities; arrays; data retention; multi-level; RRAM
DDC: 620
License: CC BY 4.0 Unported
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