Please use this identifier to cite or link to this item: https://oar.tib.eu/jspui/handle/123456789/5462
Title: Phase noise and jitter modeling for fractional-N PLLs
Authors: Osmany, S.A.Herzel, F.Schmalz, K.Winkler, W.
Publishers Version: https://doi.org/10.5194/ars-5-313-2007
Issue Date: 2007
Published in: Advances in Radio Science Vol. 5 (2007)
Publisher: Göttingen : Copernicus
Abstract: We present an analytical phase noise model for fractional-N phase-locked loops (PLL) with emphasis on integrated RF synthesizers in the GHz range. The noise of the crystal reference, the voltage-controlled oscillator (VCO), the loop filter, the charge pump, and the sigma-delta modulator (SDM) is filtered by the PLL operation. We express the rms phase error (jitter) in terms of phase noise of the reference, the VCO phase noise and the third-order loop filter parameters. In addition, we consider OFDM systems, where the PLL phase noise is reduced by digital signal processing after down-conversion of the RF signal to baseband. The rms phase error is discussed as a function of the loop parameters. Our model drastically simplifies the noise optimization of the PLL loop dynamics.
Keywords: Circuit oscillations; Delta modulation; Delta sigma modulation; Digital signal processing; Jitter; Modulators; Orthogonal frequency division multiplexing; Oscillistors; Phase locked loops; Signal processing; Space division multiple access; Variable frequency oscillators; Down conversion; Fractional-N phase-locked loops; Loop dynamics; Loop parameters; Noise optimization; Phase noise modeling; RF synthesizer; Sigma-delta modulator; Phase noise
DDC: 530
License: CC BY-NC-SA 2.5 Unported
Link to License: https://creativecommons.org/licenses/by-nc-sa/2.5/
Appears in Collections:Physik



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